sequential


Can a D flip flop be enabled this way?


Here is a D flip-flop with a CLOCK ENABLE input.
click here, I am new, can't post images yet, sry
This makes me wonder. Why not just AND gate the CLOCK and the CLOCK ENABLE inputs and output this to the flip flop clock input.
I feel like I cannot do this because the clock is somehow special, but on paper, this seems to work the same way. So if this isn't right, why?
You can do it using an AND gate (between the clock and clock enable) and removing the Multiplexer just like you're proposing. Please remember that there is no single way of solving any digital design problem. Be creative.
On the negative side of this implementation, adding a gate in the clock path (the AND gate) would mean that the clock would be delayed (due to the delay from the gate). In a more complex system, it would be a problem because the clock would not be in phase for all the components using it (this flip flop will have a delayed version of the clock).

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